In recent years, various resolutions have appeared for pixel display units such as a liquid crystal panel and a PDP, and the clock frequency for driving such panel differs from panel to panel. In a clock generation circuit or a video signal processing which can generate a clock according to the clock frequency for operating a panel, it is necessary to display video on a pixel display unit after switching to the clock frequency of the panel.
For example, in a clock generation circuit of a conventional video signal processing apparatus described in Japanese Published Patent Application No. 2000-312328 (Patent Document 1), a circuit for frequency-dividing an input clock is constituted, or a counter circuit starts operation at every reset, and a decoded value of the counter circuit is outputted as a clock.
Hereinafter, the clock generation circuit in the conventional video signal processing apparatus will be described.
FIG. 7 is a block diagram illustrating the clock generation circuit in the conventional video signal processing apparatus disclosed in Patent Document 1.
With reference to FIG. 7, the clock generation circuit has a first clock generation circuit comprising a divide-by-two frequency divider 25, and a second clock generation circuit 11 comprising a frequency setting register 20, an addition circuit 21, an AND gate 22, a flip-flop 23, and a reset generation circuit 24.
The frequency setting register 20 has a predetermined set value, and varies the set value to vary the frequency of the output clock so that the frequency of the output clock becomes smaller than the frequency of the input clock.
A counter comprises the addition circuit 21, the AND gate 22, and the flip-flop 23, and the count value of the counter is reset by a horizontal sync signal as a reset signal.
Hereinafter, the operation of the clock generation circuit constituted as described above will be described.
In the first clock generation circuit 8, a clock which is frequency-divided by two using the frequency divider 25 that is operated at the rising timing of the input clock is regarded as an output clock 1. Further, in the second clock generation circuit 11, the reset generation circuit 24 generates a reset signal from the supplied horizontal sync signal HD, at the rising timing of the input clock which is a reset input to the circuit 24 and, at this timing, the value of the frequency setting register 20 is added to the output clock 2 by the adder 21 to perform counting, and the most significant bit of the count value is used as the output clock 2 through the AND gate 22 and the latch 23, thereby varying the frequency of the output clock. The output clock 1 generated by the first clock generation circuit 8 and the output clock 2 generated by the second clock generation circuit 11 have difference numbers of cycles in one horizontal scanning period, and data are written by the output clock 1 generated by the first clock generation circuit 8 while the data are read by the output clock 2 generated by the second clock generation circuit 11.
In the clock generation circuit of the conventional video signal processing circuit, however, when resetting the counter with the reset signal which is generated by the horizontal sync signal at the clock outputted from the second clock generation circuit, if a horizontal sync signal that is an integer multiple of the cycle of the output clock is not inputted or if the input clock is a non-standard signal having a deteriorated sync signal such as VTR, the length of the clock cycle is undesirably shortened or the ratio between the Low period and the High period of the clock, i.e., the duty ratio, undesirably loses accuracy. Therefore, when the conventional clock generation circuit is applied to the video signal processing apparatus, in the processing circuit that is operated with the second clock, a timing error occurs in a combination circuit due to the short clock cycle, leading to outputting of unexpected data.
Further, in the clock generation circuit of the conventional video signal processing circuit, since the count value is reset by the horizontal sync signal, the length of the clock cycle is undesirably shortened depending on the timing at which the horizontal sync signal is inputted, leading to discontinuous output clocks.
Furthermore, in the clock generation circuit of the conventional video signal processing apparatus, it is necessary to input a high-frequency clock as an input clock. Therefore, when the clock frequency for driving a liquid crystal panel exceeds 80 MHz or 100 MHz, it is necessary for the clock oscillator to input a clock of a frequency higher than that of the panel driving clock, resulting in a noise source as well as an increase in power consumption. Accordingly, the conventional clock generation circuit is not practical.
Moreover, it may be thought that the second clock is generated from the horizontal sync signal using a high-power multiply PLL circuit. In this case, the frequency of the horizontal sync signal varies depending on the input video signal, and the output frequency differs from panel to panel, and therefore, the range of output frequencies should be secured broadly. Accordingly, it is necessary to perform verification with many combinations when a high-power multiply PLL is designed, leading to a lot of time required for designing. Further, it is difficult to reduce jitters of clocks, and redesign is needed at every miniaturization of semiconductor processing.